1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a double data rate (DDR) semiconductor memory device and a data read method of the same.
2. Description of the Related Art
A conventional double data rate (DDR) semiconductor memory device includes a first circuit that latches and outputs data from a memory cell array responsive to a first control signal and a second circuit that latches and outputs data from the first circuit responsive to a second control signal. The first control signal is generated responsive to an external clock signal. The second control signal is generated responsive to a buffered clock signal that is generated from an internal clock signal generating circuit.
As with all power supplies, the power supply of the DDR semiconductor memory device has a range of possible voltage outputs. It may be at its normal, nominal, value. Or depending on other conditions may drop slightly below its nominal value, to a low power supply voltage. Or the output voltage may drop slightly above its nominal value, to a high power supply voltage. Similarly, the temperature of the DDR semiconductor memory is not constant and may move through a range. This variation in power supply voltage and circuit temperature effects the operation of the memory device. For example, a column selecting signal and the first control signal, which are dependant on an externally-applied clock signal, are advanced at high power supply voltage and low temperature. On the other hand, the buffered clock signal and the second control signal, which are dependant on an internal clock signal, are delayed at high power supply voltage and low temperature.
This is because the internal clock signal generating circuit includes a delay locked loop (DLL) or a phase locked loop (PLL) and is designed such that these circuits either advance or delay the buffered clock signal according to variations of power supply voltage and temperature so that data can be outputted at an exact time. That is, compared to normal operation, the internal clock signal generating circuit operates to delay the buffered clock signal at high power supply voltage and low temperature which can advance the first control signal. On the other hand, at low power supply voltage and high temperature the internal clock signal generating circuit operates to advance the buffered clock signal which can delay the first control signal.
However, a problem is created at high power supply voltage and low temperature in that the first control signal is advanced and the second control signal is delayed. This causes the first and second control signals to overlap, leading to data read errors.
FIG. 1 is a block diagram illustrating a conventional DDR semiconductor memory device. The DDR semiconductor memory device of FIG. 1 includes a memory cell array 10 having a first (odd) memory bank and a second (even) memory bank, a column decoder 12, sense amplifiers 14-1 and 14-2, multiplexers 16-1 and 16-2, data output buffers 18-1 and 18-2, a data output driver 20, a first control signal generating circuit 22, an internal clock signal generating circuit 24, and a second control signal generating circuit 26.
In FIG. 1, SA denotes the sense amplifiers 14-1 and 14-2, DBMUX denotes the multiplexers 16-1 and 16-2, DOB denotes the data output buffers 18-1 and 18-2, and DOD denotes the data output driver 20.
The DDR semiconductor memory device of FIG. 1 operates as follows. The first and second memory banks read data from memory cells selected by a word line (not shown) and a bit line (not shown). The first and second memory banks then output a data DOO and DOE, respectively.
A clock signal CLK is generated by buffering a clock signal applied from an external portion. The column decoder 12 decodes an address Ai applied from an external portion to generate a column selecting signal CSL responsive to the clock signal CLK. The sense amplifiers 14-1 and 14-2 amplify the data DOO and DOE to output first data FDOO and FDOE, respectively, responsive to a first control signal FRP. The multiplexers 16-1 and 16-2 latch the first data FDOO and FDOE to output a second data SDOO and SDOE, respectively, responsive to a second control signal SRP. The data output buffers 18-1 and 18-2 buffer the data SDOO and SDOE to generate data DQO and DQE, respectively, responsive to buffered clock signals CLKDQF and CLKDQS. The data output driver 20 drives the data DQO and DQE to generate an output data DQ. The first control signal generating circuit 22 generates the first control signal FRP responsive to the clock signal CLK. The internal clock signal generating circuit 24 generates the buffered clock signals CLKDQF and CLKDQS responsive to the clock signal CLK. The internal clock signal generating circuit 24 may be composed of a Delay Locked Loop (DLL) or a Phase Locked Loop (PLL). The second control signal generating circuit 26 receives the buffered clock signal CLKDQF to generate the second control signal SRP.
FIG. 2 is a schematic view of the second control signal generating circuit of the conventional DDR semiconductor memory device. The second control signal generating circuit of FIG. 2 includes an inversion and delay circuit 40 and a NOR gate NOR1.
The second control signal generating circuit of FIG. 2 operates as follows. The inversion and delay circuit 40 inverts the buffered clock signal CLKDQF and delays it for a predetermined time period. The NOR gate NOR1 NORs an output signal of the inversion and delay circuit 40 and the buffered clock signal CLKDQF to generate the second control signal SRP. The second control signal SRP has a pulse width set by the length of time the buffered clock signal CLKDQF is delayed by the invert and delay circuit 40 and is responsive to a falling transition of the buffered clock signal CLKDQF.
As shown in FIGS. 1 and 2, the conventional DDR semiconductor memory device generates the column selecting signal CSL and the first control signal FRP by using the external clock signal CLK while the second control signal SRP and the buffered clock signals CLKDQF and CLKDQS are generated by using the internal clock signal generating circuit. Thus, the column selecting signal CSL and the first control signal FRP move in opposite directions from the second control signal SRP and the buffered clock signals CLKDQF and CLKDQS based on a variation in a power supply voltage and temperature.
FIG. 3 is a timing diagram of a read operation of the semiconductor memory device of FIG. 1 operating with an adequate power supply voltage and at room temperature (normal operating conditions), where a read command RD is applied, and after 2.5 clock cycles data is outputted to an external portion with a burst length of 4.
When a read command RD is applied responsive to a rising edge of a clock signal CLK, the column decoder 12 generates a column selecting signal CSL responsive to the clock signal CLK. The first and second memory banks sequentially output data DOO1 and DOE1 and data DOO2 and DOE2 responsive to the column selecting signal CSL, respectively. The sense amplifiers 14-1 and 14-2 sequentially amplify the data DOO1 and DOE1 and the data DOO2 and DOE2 to sequentially output a data FDOO1 and FDOE1 and a data FDOO2 and FDOE2, respectively, responsive to a first control signal FRP. The multiplexers 16-1 and 16-2 sequentially latch the data FDOO1 and FDOE1 and the data FDOO2 and FDOE2 to sequentially generate a data SDOO1 and SDOE1 and a data SDOO2 and SDOE2, respectively, responsive to a second control signal SRP.
The data output buffers 18-1 and 18-2 sequentially buffer the data SDOO1 and SDOE1 and the data SDOO2 and SDOE2 to sequentially output a data DQO1 and DQE1 and a data DQO2 and DQE2, respectively, responsive to the buffered clock signals CLKDQF and CLKDQS. The data output driver 20 sequentially drives the data DQO1 and DQE1 and the data DQO2 and DQE2 outputted from the data output buffers 18-1 and 18-2 to generate output data DQ1 to DQ4.
FIG. 4 is a timing diagram illustrating a read operation of the semiconductor memory device of FIG. 1 operating under high power supply voltage and low temperature conditions. When a read command RD is applied, and after 2.5 clock cycles data is outputted to an external portion with a burst length of 4. The dotted lines of FIG. 4 denote when the signals of FIG. 3 are generated.
As shown in FIG. 4, when the semiconductor memory device operates at a high power supply voltage and low temperature, the column selecting signal CSL and the first control signal FRP, which are generated responsive to a clock signal CLK, are advanced compared to that of FIG. 3. One the other hand the buffered clock signals CLKDQF and CLKDQS and the second control signal SRP are delayed compared to that of FIG. 3. Therefore, there exists a time period T1 when the second pulse of the first control signal FRP and the first pulse of the second control signal SRP overlap. Therefore, the data SDOO1 and SDOE1, which are outputted responsive to the first pulse of the second control signal SRP, are not transmitted completely, but the data SDOO2 and SDOE2, which are outputted responsive to the first pulse of the second control signal SRP, are transmitted completely. Also, the data DQO1 generated responsive to the first pulse of the buffered clock signal CLKDQF is not transmitted completely, and the data DQE1 generated responsive to the first pulse of the buffered clock signal CLKDQS is not transmitted. Consequently, the order of the output data is changed, and the output data DQ2 is not generated, leading to a data read error. The origin of the data error is the overlap of the second pulse of the first control signal FRP and the first pulse of the second control signal SRP.
FIG. 5 is a timing diagram illustrating a read operation of the semiconductor memory device of FIG. 1 operating under low power supply voltage and high temperature conditions. When a read command RD is applied, and a data is outputted to an external portion after 2.5 clock cycles with a burst length of 4. Dotted lines of FIG. 5 denote when signals of FIG. 3 are generated.
As shown in FIG. 5, when the semiconductor memory device operates under low power supply voltage and high temperature conditions, the column selecting signal CSL and the first control signal FRP, which are generated responsive to the external clock signal CLK, are delayed compared to that of FIG. 3. On the other hand, the buffered clock signals CLKDQF and CLKDQS and the second control signal SRP are advanced compared to that of FIG. 3. Therefore, there exists a time period T2 when the first pulse of the first control signal FRP and the first pulse of the second control signal SRP overlap.
However, in this case, responsive to the second control signal SRP, the data SDOO1 and SDOE1 and the data SDOO2 and SDOE2 are completely latched and then outputted, whereby the output data DQ1 to DQ4 are sequentially outputted.
As described above, the conventional DDR semiconductor memory device does not cause a data read error operating under normal conditions or low power supply voltage and high temperature conditions but does causes a data read error operating under high power supply voltage and low temperature conditions. This data read error occurs when an overlap occurs between the (n+1)th pulse of the first control signal FRP and the nth pulse of the second control signal SRP.